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Text File  |  1991-03-01  |  19KB  |  345 lines
  1.         TTL       M68300 BUSINESS CARD COMPUTER TABLE INIT
  2.         OPT       P=68332             SETUP FOR 68332 CODE
  3.         OPT       BRS                 SHORT BRANCHES PREFERED
  4. *
  5. ************************************************************************
  6. *** EXPORTED PORTION OF THE MODULE HEADER                            ***
  7. *V**********************************************************************
  8. ************************************************************************
  9. ***                                                                  ***
  10. *** MODULE :       TABLE INITIALIZATION                              ***
  11. ***                                                                  ***
  12. *** ENVIRONMENT :  Any CPU32 based computer system.                  ***
  13. ***                                                                  ***
  14. *** LANGUAGE :     CPU32 ASSEMBLY LANGUAGE                           ***
  15. ***                                                                  ***
  16. *** SUMMARY OF CONTENTS :                                            ***
  17. ***     INIT_T1 - a Power On Branch Vector routine to perform memory ***
  18. ***               initialization.  Returns to the PWR_INI routine    ***
  19. ***               with [A6] = Initialization Table #2 start address, ***
  20. ***               i.e., the location after the <ADDR> field that     ***
  21. ***               terminated the routine.                            ***
  22. ***                                                                  ***
  23. ***     INIT_T2 - a Power On Branch Vector routine to perform memory ***
  24. ***               initialization.  Returns to the PWR_TTL routine.   ***
  25. ***               Upon entry, [A6] = Initialization Table #2 start   ***
  26. ***               address.                                           ***
  27. ***                                                                  ***
  28. ***     The Initialization Table is organized as a series of entries ***
  29. ***     each of which has the follow format:                         ***
  30. ***                                                                  ***
  31. ***             <ADDR><CNT/SZ><FILL><DATA>                           ***
  32. ***                 4       1    0|1    n       <--- # bytes         ***
  33. ***     Where:                                                       ***
  34. ***            <ADDR>   is the destination address for the <DATA>.   ***
  35. ***                     It is 4 bytes long and must start on a even  ***
  36. ***                     address (word) boundary.  A value equal to   ***
  37. ***                     the FILL.L value terminates the routine.     ***
  38. ***                                                                  ***
  39. ***            <CNT/SZ> is the count/size code for the <DATA> and is ***
  40. ***                     encoded as "$ns" where:                      ***
  41. ***                        n   is the upper nibble and contains the  ***
  42. ***                            count value minus one for number of   ***
  43. ***                            <DATA> elements of size "s" that are  ***
  44. ***                            to be stored in successive addresses, ***
  45. ***                            starting with <ADDR>.                 ***
  46. ***                        s   is the lower nibble and contains the  ***
  47. ***                            size code for the <DATA> and the      ***
  48. ***                            storage operation itself.  Valid size ***
  49. ***                            codes are as follows:                 ***
  50. ***                                     1 = BYTE data                ***
  51. ***                                     2 = WORD data                ***
  52. ***                                     4 = LONG WORD data           ***
  53. ***                            An invalid size code terminates the   ***
  54. ***                            routine.                              ***
  55. ***                                                                  ***
  56. ***            <FILL>   is a dummy placeholder/filler that is only   ***
  57. ***                     present for WORD and LONG WORD sized <DATA>  ***
  58. ***                     so they will be aligned on an even address   ***
  59. ***                     (word) boundary.  Thus the fill byte is not  ***
  60. ***                     present for BYTE data, otherwise it is one   ***
  61. ***                     byte long.                                   ***
  62. ***                                                                  ***
  63. ***             <DATA>  is the byte, word, or long word data as      ***
  64. ***                     specified by <CNT/SZ> that is to be stored   ***
  65. ***                     starting at <ADDR>.  This field contains     ***
  66. ***                     exactly s*(n+1) data bytes.  If the data     ***
  67. ***                     size is BYTE (s=1) and there are an even     ***
  68. ***                     number of <DATA> elements (n=odd), then one  ***
  69. ***                     filler byte is added so the next Table entry ***
  70. ***                     will start on an even address (word)         ***
  71. ***                     boundary.                                    ***
  72. ***                                                                  ***
  73. ***     This entry format aligns with the normal assembler output,   ***
  74. ***     as DC.W and DC.L are automatically aligned on an an even     ***
  75. ***     address (word) boundary, as seen in the examples below.      ***
  76. ***     Thus the <FILL> byte is handled automatically by the assem-  ***
  77. ***     bler!                                                        ***
  78. ***                                                                  ***
  79. ***             Rel.                                                 ***
  80. ***             Addr Contents   Label   Opcode  Operand  Comment     ***
  81. ***             ---- ---------  -----   ------  -------  ----------- ***
  82. ***             0000 00FFFFA21          DC.L    $FFFFA21   <ADDR>    ***
  83. ***             0004 01                 DC.B    1        1 BYTE DATA ***
  84. ***             0005 04                 DC.B    $04        <DATA>    ***
  85. ***                                                                  ***
  86. ***             0006 00FFFFA21          DC.L    $FFFFA21   <ADDR>    ***
  87. ***             000A 31                 DC.B    $31      4 BYTE DATA ***
  88. ***             000B 04 22 47 FE        DC.B    $04,$22,$47,$FE      ***
  89. ***                                                                  ***
  90. *** Skips $1F-> 0010 00FFFFA22          DC.L    $FFFFA22   <ADDR>    ***
  91. ***             0014 02                 DC.B    2        1 WORD DATA ***
  92. *** Skips $15-> 0016 0544               DC.W    $0544      <DATA>    ***
  93. ***                                                                  ***
  94. ***             0018 00FFFFA74          DC.L    $FFFFA74   <ADDR>    ***
  95. ***             001C 04                 DC.B    4        1 LONG DATA ***
  96. *** Skips $1D-> 001E 12345678           DC.L    $12345678  <DATA>    ***
  97. ***                                                                  ***
  98. ***             0022 00FFFFA74          DC.L    $FFFFA74   <ADDR>    ***
  99. ***             0026 04                 DC.B    $14      2 LONG DATA ***
  100. *** Skips $27-> 0028 12345678           DC.L    $12345678,$2307F     ***
  101. ***             002C 0002307F                                        ***
  102. ***                                                                  ***
  103. ***             0030 FFFFFFFF           DC.L    $FFFFFFFF Terminate  ***
  104. ***                                                                  ***
  105. ***     The routine will also terminate before any attempt is made   ***
  106. ***     to read table information past the end of the table.  Thus   ***
  107. ***     the user can completely fill the table without having to     ***
  108. ***     have a termination entry whose <ADDR> equals FILL.L.         ***
  109. ***                                                                  ***
  110. ***  CAUTIONS:                                                       ***
  111. ***   1. The user should never use the Initialization Table to       ***
  112. ***      alter the SYPCR or MCR registers, as the AND values in      ***
  113. ***      the parameter area (SYPCR_AND, MCR_AND) are used to         ***
  114. ***      determine if the software watchdog is active and where      ***
  115. ***      the register module base address is located ($00FFF000 or   ***
  116. ***      $007FF000?).  Similarly, the CSBOOT option register value   ***
  117. ***      in the parameter area (.CSORBT) is used to change the       ***
  118. ***      DSACK* field from 13 wait cycles to the user specified      ***
  119. ***      value as quickly as possible so booting in 8-bit mode       ***
  120. ***      will function and to make the code execute as quickly as    ***
  121. ***      possible by eliminating unnecessary wait states.            ***
  122. ***                                                                  ***
  123. *** LINK REQUIREMENTS :                                              ***
  124. ***                                                                  ***
  125. ************************************************************************
  126. *^**********************************************************************
  127. *
  128.          PAGE
  129. *
  130. ************************************************************************
  131. *** INTERNAL PORTION OF THE MODULE HEADER                            ***
  132. ************************************************************************
  133. ***                                                                  ***
  134. ***   REVISION HISTORY (add changes to the top):                     ***
  135. ***                                                                  ***
  136. ***      DATE         AUTHOR               CHANGES                   ***
  137. ***   ----------  ---------------  --------------------------------  ***
  138. ***    03/01/91   Peter S. Gilmour Initial version port to MS_DOS    ***
  139. ***                                based M68MASM from original source***
  140. ***                                code.  Compatible with CPU32Bug   ***
  141. ***                                version 1.00.                     ***
  142. ************************************************************************
  143. *** XDEFS :                                                          ***
  144.         XDEF    INIT_T1
  145.         XDEF    INIT_T2
  146. ***                                                                  ***
  147. *** XREFS :                                                          ***
  148.         XREF    PWR_INI
  149.         XREF    PWR_TTL
  150.         XREF    INITTBL
  151.         XREF    INITTBLE
  152.         XREF    .CSBARBT
  153.         XREF    SYPCR_AND
  154.         XREF    MCR_AND
  155. ***                                                                  ***
  156. ***   Local macros:                                                  ***
  157. ***                                                                  ***
  158. SYSTEM   MACRO                         ! SETUP MONITOR SPACE
  159. SECTD    SET       1                   ! DEFINE DATA SECTION
  160. SECTP    SET       14                  ! DEFINE PROGRAM SECTION
  161.          SECTION   SECTP               ! PUT USER INTO PROG. SECTION
  162.          ENDM                          !
  163.  
  164. LEA32PCR MACRO     LABEL
  165.          LEA       (*+4,PC),\2
  166.          ADDA.L    #\1-*,\2
  167.          ENDM
  168.  
  169. ***
  170. ***   Local equates:
  171. ***
  172. *
  173. *  For M68300 BCC and PFB.
  174. *
  175. *  NOTE: Unused upper address lines are specified as 1's so ABSOLUTE SHORT
  176. *        addressing (sign extension) can be used.
  177. *
  178. SR_VAL    EQU      $2700               Status register initial value.
  179.  
  180. HI_BASE  EQU       $FFFFF000           CPU32 module (registers) base high addr
  181. *                                      .  This is the default used at power-up!
  182. LO_BASE  EQU       $007FF000           CPU32 module (registers) base low  addr
  183. SIM      EQU       $A00                CPU32 System Integration Module base addr
  184. MCR      EQU       SIM+$00             Module Control Register
  185. MM_BIT   EQU       6                   .  MM bit number              in MCR
  186. SYPCR    EQU       SIM+$20             System Protection Control Register
  187. SWE_BIT  EQU       7                   .  SWE bit number                in SYPCR
  188. SWSR     EQU       SIM+$27             Software Service Reg (WATCHDOG) = BYTE
  189. WATCHV1  EQU       $55                 .  Software Watchdog value #1
  190. WATCHV2  EQU       $AA                 .  Software Watchdog value #2
  191. CSBARBT  EQU       SIM+$48             Chip Select Base Boot Register
  192.  
  193. ROMUNPGM  EQU      $FF                 unprogrammed state of a byte of EPROM
  194. FILL.1    EQU      ROMUNPGM            fill value for 1 byte = BYTE
  195. FILL.2    EQU      FILL.1<<8+FILL.1    fill value for 2 bytes= WORD
  196. FILL.4    EQU      FILL.2<<16+FILL.2   fill value for 4 bytes= LONG WORD
  197.  
  198.  
  199. BYTESIZE EQU    1                  <SIZE> code for BYTE data
  200. WORDSIZE EQU    2                  <SIZE> code for WORD data
  201. LONGSIZE EQU    4                  <SIZE> code for LONG WORD data
  202. MINENTSZ EQU    -(4+1+0+1)         Size of smallest possible Table entry
  203. * <ADDR> = 4 bytes, <SIZE> = 1 byte, <FILL> = 0 bytes, <DATA> = 1 byte
  204.  
  205.         SYSTEM
  206.  
  207. * Start Initialization Table #1 Processing:
  208. *   - exits with [A6] = Init Table #2 starting address
  209. *   - preserves D7.L (flag register)
  210. *   - presumes Software Watchdog is not active!
  211. *   - returns to PWR_INI
  212. *
  213. INIT_T1:
  214.         MOVE.W    #SR_VAL,SR       Ensure status register initialized.
  215.  
  216. * Set up CSBOOT CHIP SELECT:
  217. *  - Long word also gets .CSORBT value into CSORBT register!
  218. *  - Set up wait cycles for Boot ROM so this code can execute at
  219. *    full speed!
  220. *
  221.         MOVE.L    ((.CSBARBT).L,PC),CSBARBT+HI_BASE
  222.  
  223.         LEA32PCR  INITTBL,A6       [A6]= Init Table #1 starting address
  224.         LEA32PCR  PWR_INI,A1       [A1]= Init Table #1 return   address
  225.         MOVEQ.L   #0,D3            [D3]= Table #2 flag: 0= false, else= true
  226.         BRA.S     INIT_TBL
  227.  
  228.  
  229. * Start Initialization Table #2 Processing:
  230. *   - enter with [A6] = Init Table #2 starting address
  231. *   - preserves D7.L (flag register)
  232. *   - handles Software Watchdog which may be active after PWR_INI call!
  233. *   - returns to PWR_TTL
  234. *
  235. INIT_T2:
  236. *           [A6]= Init Table #2 starting address
  237.         LEA32PCR  PWR_TTL,A1       [A1]= Init Table #2 return   address
  238.         MOVEQ.L   #1,D3            [D3]= Table #2 flag: 0= false, else= true
  239.  
  240. * Common Initialize Table code:
  241. *
  242. INIT_TBL:
  243.         LEA32PCR  INITTBLE,A4      [A4]= Init Table end (1st invalid addr)
  244.         LEA       (MINENTSZ,A4),A3 [A3]= addr of last possible Table entry
  245. * <ADDR> = 4 bytes, <SIZE> = 1 byte, <FILL> = 0 bytes, <DATA> = 1 byte
  246.         LEA       (-4,A4),A2       [A2]= addr of last possible LONG WORD data
  247.         MOVE.L    #FILL.4,D2       [D2]= TERMINATE value for address.
  248.  
  249. TBL_NXT:
  250. *  If processing Init. Table #2, then
  251. *    If Software Watchdog enabled, then
  252. *      Find register block location: high or low address
  253. *      Service the watchdog registers @ proper address
  254. *    endif
  255. *  endif
  256. *
  257.         TST.L     D3
  258.    IF  <NE>  THEN.S                          If doing Init. Table #2, then...
  259.         BTST      #SWE_BIT,((SYPCR_AND).L,PC)
  260.         IF  <NE>  THEN.S                     .  If s/w watchdog enabled, then...
  261.            BTST      #MM_BIT,((MCR_AND+1).L,PC)
  262.            IF  <NE>  THEN.S                  .    If module regs are high, then...
  263.              MOVE.B    #WATCHV1,SWSR+HI_BASE .      Service watchdog @ high mem
  264.              MOVE.B    #WATCHV2,SWSR+HI_BASE
  265.            ELSE.S                            .    else module regs are low, so...
  266.              MOVE.B    #WATCHV1,SWSR+LO_BASE .      Service watchdog @ low mem
  267.              MOVE.B    #WATCHV2,SWSR+LO_BASE
  268.            ENDI
  269.         ENDI
  270.    ENDI
  271.         CMP.L     A3,A6
  272.         BHI.S     TBL_XIT          Branch if past last possible table entry!
  273.  
  274.         MOVE.L    (A6)+,A0         Get next address value.
  275.         CMP.L     A0,D2
  276.         BEQ.S     TBL_XIT          Branch if address equals TERMINATE value!
  277.         MOVEQ.L   #0,D0
  278.         MOVE.B    (A6)+,D0         Otherwise get count/size code.
  279.         MOVE.W    D0,D1
  280.         LSR.W     #4,D1            Set [D1.W]= count value - 1 (for DBRA loop).
  281.         AND.B     #$0F,D0          Set [D0.B]= size code.
  282.         CMP.B     #BYTESIZE,D0
  283.         BEQ.S     TBL_BYTE         Branch if BYTE sized data present!
  284.         ADDA.L    #1,A6            Skip <FILL> data location.
  285. *                                  . Aligns to even address boundary for
  286. *                                  . accessing WORD or LONGWORD data!
  287.         CMP.B    #WORDSIZE,D0
  288.         BEQ.S    TBL_WORD          Branch if WORD sized data present!
  289.         CMP.B    #LONGSIZE,D0
  290.         BEQ.S    TBL_LONG          Branch if LONG WORD sized data present!
  291. * Exit if invalid code size found!
  292.  
  293. * Here to exit:
  294. *
  295. TBL_XIT:
  296.         JMP      (A1)              Return to Power On Branch Vector
  297. * [D7.L] = preserved!
  298.  
  299.  
  300. *----------------------------------------------------------------------------
  301. * Here for LONG WORD data:
  302. *
  303. TBL_LONG:
  304.         CMP.L    A2,A6
  305.         BHI      TBL_XIT           Branch if past last possible LONG WORD.
  306.  
  307.         MOVE.L   (A6)+,(A0)        Otherwise move LONG value to address.
  308.         DBRA     D1,TBL_LONG       Continue until count LONGs are moved...
  309.  
  310.         BRA      TBL_NXT           Continue until table exhausted!
  311.  
  312.  
  313. *----------------------------------------------------------------------------
  314. * Here for WORD data:
  315. *
  316. TBL_WORD:
  317.         CMP.L    A4,A6
  318.         BHS      TBL_XIT           Branch if past last possible WORD.
  319.  
  320.         MOVE.W   (A6)+,(A0)        Otherwise move WORD value to address.
  321.  
  322.         DBRA     D1,TBL_WORD       Continue until count WORDs are moved...
  323.         BRA      TBL_NXT           Continue until table exhausted!
  324.  
  325.  
  326. *----------------------------------------------------------------------------
  327. * Here for BYTE data:
  328. *
  329. TBL_BYTE:
  330.         CMP.L    A4,A6
  331.         BHS      TBL_XIT           Branch if past last possible BYTE.
  332.  
  333.         MOVE.B   (A6)+,(A0)        Move BYTE value to address.
  334.         DBRA     D1,TBL_BYTE       Continue until count BYTEs are moved...
  335.  
  336.         MOVE.L   A6,D0             Check for ODD ending Table address.
  337.         BTST     #0,D0
  338.         BCC      TBL_NXT           If EVEN Table address, continue...
  339.         ADD      #1,A6             Otherwise make Table address even and
  340. *                                  .  (i.e., skip FILLER byte!)
  341.         BRA      TBL_NXT           Continue until table exhausted!
  342.  
  343.  
  344.         END
  345.