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INITTBL.SA
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1991-03-01
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19KB
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345 lines
TTL M68300 BUSINESS CARD COMPUTER TABLE INIT
OPT P=68332 SETUP FOR 68332 CODE
OPT BRS SHORT BRANCHES PREFERED
*
************************************************************************
*** EXPORTED PORTION OF THE MODULE HEADER ***
*V**********************************************************************
************************************************************************
*** ***
*** MODULE : TABLE INITIALIZATION ***
*** ***
*** ENVIRONMENT : Any CPU32 based computer system. ***
*** ***
*** LANGUAGE : CPU32 ASSEMBLY LANGUAGE ***
*** ***
*** SUMMARY OF CONTENTS : ***
*** INIT_T1 - a Power On Branch Vector routine to perform memory ***
*** initialization. Returns to the PWR_INI routine ***
*** with [A6] = Initialization Table #2 start address, ***
*** i.e., the location after the <ADDR> field that ***
*** terminated the routine. ***
*** ***
*** INIT_T2 - a Power On Branch Vector routine to perform memory ***
*** initialization. Returns to the PWR_TTL routine. ***
*** Upon entry, [A6] = Initialization Table #2 start ***
*** address. ***
*** ***
*** The Initialization Table is organized as a series of entries ***
*** each of which has the follow format: ***
*** ***
*** <ADDR><CNT/SZ><FILL><DATA> ***
*** 4 1 0|1 n <--- # bytes ***
*** Where: ***
*** <ADDR> is the destination address for the <DATA>. ***
*** It is 4 bytes long and must start on a even ***
*** address (word) boundary. A value equal to ***
*** the FILL.L value terminates the routine. ***
*** ***
*** <CNT/SZ> is the count/size code for the <DATA> and is ***
*** encoded as "$ns" where: ***
*** n is the upper nibble and contains the ***
*** count value minus one for number of ***
*** <DATA> elements of size "s" that are ***
*** to be stored in successive addresses, ***
*** starting with <ADDR>. ***
*** s is the lower nibble and contains the ***
*** size code for the <DATA> and the ***
*** storage operation itself. Valid size ***
*** codes are as follows: ***
*** 1 = BYTE data ***
*** 2 = WORD data ***
*** 4 = LONG WORD data ***
*** An invalid size code terminates the ***
*** routine. ***
*** ***
*** <FILL> is a dummy placeholder/filler that is only ***
*** present for WORD and LONG WORD sized <DATA> ***
*** so they will be aligned on an even address ***
*** (word) boundary. Thus the fill byte is not ***
*** present for BYTE data, otherwise it is one ***
*** byte long. ***
*** ***
*** <DATA> is the byte, word, or long word data as ***
*** specified by <CNT/SZ> that is to be stored ***
*** starting at <ADDR>. This field contains ***
*** exactly s*(n+1) data bytes. If the data ***
*** size is BYTE (s=1) and there are an even ***
*** number of <DATA> elements (n=odd), then one ***
*** filler byte is added so the next Table entry ***
*** will start on an even address (word) ***
*** boundary. ***
*** ***
*** This entry format aligns with the normal assembler output, ***
*** as DC.W and DC.L are automatically aligned on an an even ***
*** address (word) boundary, as seen in the examples below. ***
*** Thus the <FILL> byte is handled automatically by the assem- ***
*** bler! ***
*** ***
*** Rel. ***
*** Addr Contents Label Opcode Operand Comment ***
*** ---- --------- ----- ------ ------- ----------- ***
*** 0000 00FFFFA21 DC.L $FFFFA21 <ADDR> ***
*** 0004 01 DC.B 1 1 BYTE DATA ***
*** 0005 04 DC.B $04 <DATA> ***
*** ***
*** 0006 00FFFFA21 DC.L $FFFFA21 <ADDR> ***
*** 000A 31 DC.B $31 4 BYTE DATA ***
*** 000B 04 22 47 FE DC.B $04,$22,$47,$FE ***
*** ***
*** Skips $1F-> 0010 00FFFFA22 DC.L $FFFFA22 <ADDR> ***
*** 0014 02 DC.B 2 1 WORD DATA ***
*** Skips $15-> 0016 0544 DC.W $0544 <DATA> ***
*** ***
*** 0018 00FFFFA74 DC.L $FFFFA74 <ADDR> ***
*** 001C 04 DC.B 4 1 LONG DATA ***
*** Skips $1D-> 001E 12345678 DC.L $12345678 <DATA> ***
*** ***
*** 0022 00FFFFA74 DC.L $FFFFA74 <ADDR> ***
*** 0026 04 DC.B $14 2 LONG DATA ***
*** Skips $27-> 0028 12345678 DC.L $12345678,$2307F ***
*** 002C 0002307F ***
*** ***
*** 0030 FFFFFFFF DC.L $FFFFFFFF Terminate ***
*** ***
*** The routine will also terminate before any attempt is made ***
*** to read table information past the end of the table. Thus ***
*** the user can completely fill the table without having to ***
*** have a termination entry whose <ADDR> equals FILL.L. ***
*** ***
*** CAUTIONS: ***
*** 1. The user should never use the Initialization Table to ***
*** alter the SYPCR or MCR registers, as the AND values in ***
*** the parameter area (SYPCR_AND, MCR_AND) are used to ***
*** determine if the software watchdog is active and where ***
*** the register module base address is located ($00FFF000 or ***
*** $007FF000?). Similarly, the CSBOOT option register value ***
*** in the parameter area (.CSORBT) is used to change the ***
*** DSACK* field from 13 wait cycles to the user specified ***
*** value as quickly as possible so booting in 8-bit mode ***
*** will function and to make the code execute as quickly as ***
*** possible by eliminating unnecessary wait states. ***
*** ***
*** LINK REQUIREMENTS : ***
*** ***
************************************************************************
*^**********************************************************************
*
PAGE
*
************************************************************************
*** INTERNAL PORTION OF THE MODULE HEADER ***
************************************************************************
*** ***
*** REVISION HISTORY (add changes to the top): ***
*** ***
*** DATE AUTHOR CHANGES ***
*** ---------- --------------- -------------------------------- ***
*** 03/01/91 Peter S. Gilmour Initial version port to MS_DOS ***
*** based M68MASM from original source***
*** code. Compatible with CPU32Bug ***
*** version 1.00. ***
************************************************************************
*** XDEFS : ***
XDEF INIT_T1
XDEF INIT_T2
*** ***
*** XREFS : ***
XREF PWR_INI
XREF PWR_TTL
XREF INITTBL
XREF INITTBLE
XREF .CSBARBT
XREF SYPCR_AND
XREF MCR_AND
*** ***
*** Local macros: ***
*** ***
SYSTEM MACRO ! SETUP MONITOR SPACE
SECTD SET 1 ! DEFINE DATA SECTION
SECTP SET 14 ! DEFINE PROGRAM SECTION
SECTION SECTP ! PUT USER INTO PROG. SECTION
ENDM !
LEA32PCR MACRO LABEL
LEA (*+4,PC),\2
ADDA.L #\1-*,\2
ENDM
***
*** Local equates:
***
*
* For M68300 BCC and PFB.
*
* NOTE: Unused upper address lines are specified as 1's so ABSOLUTE SHORT
* addressing (sign extension) can be used.
*
SR_VAL EQU $2700 Status register initial value.
HI_BASE EQU $FFFFF000 CPU32 module (registers) base high addr
* . This is the default used at power-up!
LO_BASE EQU $007FF000 CPU32 module (registers) base low addr
SIM EQU $A00 CPU32 System Integration Module base addr
MCR EQU SIM+$00 Module Control Register
MM_BIT EQU 6 . MM bit number in MCR
SYPCR EQU SIM+$20 System Protection Control Register
SWE_BIT EQU 7 . SWE bit number in SYPCR
SWSR EQU SIM+$27 Software Service Reg (WATCHDOG) = BYTE
WATCHV1 EQU $55 . Software Watchdog value #1
WATCHV2 EQU $AA . Software Watchdog value #2
CSBARBT EQU SIM+$48 Chip Select Base Boot Register
ROMUNPGM EQU $FF unprogrammed state of a byte of EPROM
FILL.1 EQU ROMUNPGM fill value for 1 byte = BYTE
FILL.2 EQU FILL.1<<8+FILL.1 fill value for 2 bytes= WORD
FILL.4 EQU FILL.2<<16+FILL.2 fill value for 4 bytes= LONG WORD
BYTESIZE EQU 1 <SIZE> code for BYTE data
WORDSIZE EQU 2 <SIZE> code for WORD data
LONGSIZE EQU 4 <SIZE> code for LONG WORD data
MINENTSZ EQU -(4+1+0+1) Size of smallest possible Table entry
* <ADDR> = 4 bytes, <SIZE> = 1 byte, <FILL> = 0 bytes, <DATA> = 1 byte
SYSTEM
* Start Initialization Table #1 Processing:
* - exits with [A6] = Init Table #2 starting address
* - preserves D7.L (flag register)
* - presumes Software Watchdog is not active!
* - returns to PWR_INI
*
INIT_T1:
MOVE.W #SR_VAL,SR Ensure status register initialized.
* Set up CSBOOT CHIP SELECT:
* - Long word also gets .CSORBT value into CSORBT register!
* - Set up wait cycles for Boot ROM so this code can execute at
* full speed!
*
MOVE.L ((.CSBARBT).L,PC),CSBARBT+HI_BASE
LEA32PCR INITTBL,A6 [A6]= Init Table #1 starting address
LEA32PCR PWR_INI,A1 [A1]= Init Table #1 return address
MOVEQ.L #0,D3 [D3]= Table #2 flag: 0= false, else= true
BRA.S INIT_TBL
* Start Initialization Table #2 Processing:
* - enter with [A6] = Init Table #2 starting address
* - preserves D7.L (flag register)
* - handles Software Watchdog which may be active after PWR_INI call!
* - returns to PWR_TTL
*
INIT_T2:
* [A6]= Init Table #2 starting address
LEA32PCR PWR_TTL,A1 [A1]= Init Table #2 return address
MOVEQ.L #1,D3 [D3]= Table #2 flag: 0= false, else= true
* Common Initialize Table code:
*
INIT_TBL:
LEA32PCR INITTBLE,A4 [A4]= Init Table end (1st invalid addr)
LEA (MINENTSZ,A4),A3 [A3]= addr of last possible Table entry
* <ADDR> = 4 bytes, <SIZE> = 1 byte, <FILL> = 0 bytes, <DATA> = 1 byte
LEA (-4,A4),A2 [A2]= addr of last possible LONG WORD data
MOVE.L #FILL.4,D2 [D2]= TERMINATE value for address.
TBL_NXT:
* If processing Init. Table #2, then
* If Software Watchdog enabled, then
* Find register block location: high or low address
* Service the watchdog registers @ proper address
* endif
* endif
*
TST.L D3
IF <NE> THEN.S If doing Init. Table #2, then...
BTST #SWE_BIT,((SYPCR_AND).L,PC)
IF <NE> THEN.S . If s/w watchdog enabled, then...
BTST #MM_BIT,((MCR_AND+1).L,PC)
IF <NE> THEN.S . If module regs are high, then...
MOVE.B #WATCHV1,SWSR+HI_BASE . Service watchdog @ high mem
MOVE.B #WATCHV2,SWSR+HI_BASE
ELSE.S . else module regs are low, so...
MOVE.B #WATCHV1,SWSR+LO_BASE . Service watchdog @ low mem
MOVE.B #WATCHV2,SWSR+LO_BASE
ENDI
ENDI
ENDI
CMP.L A3,A6
BHI.S TBL_XIT Branch if past last possible table entry!
MOVE.L (A6)+,A0 Get next address value.
CMP.L A0,D2
BEQ.S TBL_XIT Branch if address equals TERMINATE value!
MOVEQ.L #0,D0
MOVE.B (A6)+,D0 Otherwise get count/size code.
MOVE.W D0,D1
LSR.W #4,D1 Set [D1.W]= count value - 1 (for DBRA loop).
AND.B #$0F,D0 Set [D0.B]= size code.
CMP.B #BYTESIZE,D0
BEQ.S TBL_BYTE Branch if BYTE sized data present!
ADDA.L #1,A6 Skip <FILL> data location.
* . Aligns to even address boundary for
* . accessing WORD or LONGWORD data!
CMP.B #WORDSIZE,D0
BEQ.S TBL_WORD Branch if WORD sized data present!
CMP.B #LONGSIZE,D0
BEQ.S TBL_LONG Branch if LONG WORD sized data present!
* Exit if invalid code size found!
* Here to exit:
*
TBL_XIT:
JMP (A1) Return to Power On Branch Vector
* [D7.L] = preserved!
*----------------------------------------------------------------------------
* Here for LONG WORD data:
*
TBL_LONG:
CMP.L A2,A6
BHI TBL_XIT Branch if past last possible LONG WORD.
MOVE.L (A6)+,(A0) Otherwise move LONG value to address.
DBRA D1,TBL_LONG Continue until count LONGs are moved...
BRA TBL_NXT Continue until table exhausted!
*----------------------------------------------------------------------------
* Here for WORD data:
*
TBL_WORD:
CMP.L A4,A6
BHS TBL_XIT Branch if past last possible WORD.
MOVE.W (A6)+,(A0) Otherwise move WORD value to address.
DBRA D1,TBL_WORD Continue until count WORDs are moved...
BRA TBL_NXT Continue until table exhausted!
*----------------------------------------------------------------------------
* Here for BYTE data:
*
TBL_BYTE:
CMP.L A4,A6
BHS TBL_XIT Branch if past last possible BYTE.
MOVE.B (A6)+,(A0) Move BYTE value to address.
DBRA D1,TBL_BYTE Continue until count BYTEs are moved...
MOVE.L A6,D0 Check for ODD ending Table address.
BTST #0,D0
BCC TBL_NXT If EVEN Table address, continue...
ADD #1,A6 Otherwise make Table address even and
* . (i.e., skip FILLER byte!)
BRA TBL_NXT Continue until table exhausted!
END